Synchronization between asynchronous clock domain data in veterinary B-ultrasound system. In the field of logic design, there are not many designs involving only a single clock domain. A system often has multiple driving clocks, and each clock cooperates with a certain interface to complete the entire function of the veterinary B-ultrasound system. When communicating between two clock domains, the problem of metastability must be handled well. Metastability is caused by the failure of the trigger's setup time or hold time to be met. Its harm is mainly reflected in the destruction of the stability of the system.

The communication between the two clock domains is roughly divided into data transmission communication and command interaction communication. For the cross-clock domain transmission of a large amount of data, it is best to use the internal dual-port RAM or asynchronous FIFO during the period. For the transmission of commands, usually two register samples are made in the destination clock domain, which can effectively reduce the propagation of metastable states.

The module division in the veterinary B-ultrasound system is very important, which directly determines the comprehensive design of the entire veterinary B-ultrasound system, the time consumption and efficiency of implementation. The main principles of module division are: use registers for the output of each sub-module of synchronous timing design, so that it is easier for the synthesis tool to weigh the combinational circuit part and the synchronous timing circuit part in the divided sub-module, so as to achieve better timing optimization effect, and it is also easier for the back-end to make timing constraints; divide the related logic and reusable logic into the same module, so as to reuse resources to the greatest extent, reduce the area consumed by the design, and use the synthesis tool to optimize the timing critical path of a specific function; separate the logic of different optimization targets. In the principles of FPGA design in veterinary B-ultrasound systems, there is the principle of area and speed balance. Within a design, there are often some parts that need to save area, while other parts have very high timing requirements. Dividing these two types of logic into different modules makes it easier for the synthesis and back-end implementation tools to optimize the area and timing of these two parts respectively.